The present invention relates to a semiconductor memory device, and more particularly, to a technology of generating a word line off voltage to minimize a leakage current of a cell transistor.
FIG. 1 is a circuit diagram showing a memory cell of a conventional semiconductor memory device. As shown in the drawing, a memory cell in a memory device includes a capacitor C for storing data and a cell transistor T for controlling charge sharing between the capacitor C and a bit line BL under the control of a word line WL.
Ideally, when the word line WL is enabled, the cell transistor T should be completely turned on, whereas when the word line WL is disabled, the cell transistor T should be completely turned off, thereby completely separating the capacitor C from the bit line BL electrically. However, the transistor cannot be completely turned on/off due to its characteristics. Therefore, when the word line WL is enabled, a higher voltage VPP than a power supply voltage VDD is applied to the transistor T so that it is turned on more completely.
On the other hand, when the word line WL is disabled, a lower word line off voltage VBBW than a ground voltage VSS is inputted to the transistor T so that it is turned off more completely. This is because, when the cell transistor T is turned off, an amount of leakage current should be decreased to improve refresh characteristics of the memory device.
FIG. 2 is shows details of the cell transistor T in FIG. 1. Referring to the drawing, a word line WL is disabled and a word line off voltage VBBW is applied to a gate of the cell transistor T. And, ‘high’ data is stored in a capacitor C and a core voltage VCORE is inputted to a drain VD of the cell transistor. Also, the bit line BL is precharged and a half core voltage VCORE/2 is applied to a source of the cell transistor. Furthermore, a negative voltage VBB is applied to a back bias of the cell transistor.
In this state, it is most ideal that the cell transistor T is turned off to let no current flow therethrough, but a little current actually flows through the cell transistor T. At this time, current flowing through the cell transistor includes an off current I_OFF and a leakage current I_LEAK. The off current I_OFF refers to current flowing from drain to source and the leakage current I_LEAK stands for a junction leakage current.
In order to enhance refresh characteristics of a memory device, namely to prevent data leakage, a sum of an off current I_OFF and a leakage current I_LEAK that flow when the word line is disabled has to be minimized. For this minimization, a level of the word line off voltage VBBW needs to be properly adjusted.
FIG. 3 is a graph showing that an off current I_OFF and a leakage current I_LEAK vary as a word line off voltage VBBW varies. Referring to the drawing, it has the following performance characteristics. That is, as the word line off voltage VBBW decreases (in other words, as a negative absolute value increases), the off current decreases but the leakage current rather increases.
Meanwhile, data leakage occurs, which corresponds to a total current I_TOTAL that is a sum of the off current I_OFF and the leakage current I_LEAK. Therefore, in order to reduce such data leakage, the word line off voltage VBBW that minimizes an amount of total current I_TOTAL needs to be used.
FIG. 4 is a circuit diagram showing a typical circuit for generating a word line off voltage VBB. The typical word line off voltage generation circuit generates a word line off voltage VBBW from a negative voltage VBB. The negative voltage VBB refers to a lower voltage than a ground voltage VSS, which is resulted from a pumping operation in a negative voltage pumping circuit. In general, the negative voltage VBB has a lower level than the word line off voltage VBBW.
In FIG. 4, resistors R1 and R2 are used for voltage division of a core voltage VCORE and a word line off voltage VBBW to generate a first voltage VHALF1, and resistors R3 and R4 are used for voltage division of the core voltage VCORE and a ground voltage VSS to produce a second voltage VHALF2.
The first voltage VHALF1 and the second voltage VHALF2 so generated are then applied to an operational amplifier 401, which controls a turning-on operation of a transistor N1 with its output voltage DET. As a result, the word line off voltage VBBW with a certain difference from the negative voltage VBB, i.e., with a higher level than the negative voltage is generated.
Meanwhile, a resistance ratio of the resistors R1 to R4 and a turning-on voltage of the transistor N1 can be properly adjusted based on a level of the negative voltage VBB and a level of the word line off voltage VBBW to be generated. Currently, when the negative voltage VBB level is −0.8 V, the resistance ratio and the turning-on voltage of the transistor are adjusted so that the word line off voltage VBBW level can be about −0.3 V.
As described above, the conventional word line off voltage generating circuit generates a word line off voltage VBBW with a particular value. Therefore, if an optimized word line off voltage VBBW level varies due to variations in Process, Voltage and Temperature (PVT) conditions within a memory device chip, such word line off voltage VBBW level may not vary accordingly.